1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Background Art
Recently, due to miniaturization of semiconductor devices, it is required to form a pattern including narrower lines than can be formed by lithography. In particular, although the gate electrode of a logic device requires a size of 40 nm or less, the limit of the exposing processing performed by a current ArF exposing device is about 70 nm. In order to solve this problem, a “trimming process” is employed, in which a resist pattern formed by a lithography process is trimmed by dry etching, thereby obtaining a miniaturized pattern. However, since the lines in the resist pattern are narrowed at a constant rate in this trimming process, the space portions are expanded. In order to obtain a desired space size, it is necessary to form narrower space portions in advance using a lithographic technique. However, since the required size is smaller than the limit of size that can be obtained by the lithographic technique, it is not possible to form a space portion with a sufficient sizing accuracy.
On the other hand, a technique is known in which in order to make an interval between floating gates smaller than the lithographic limit value (resolution limit value of an exposing device), an opening having a width corresponding to the lithographic limit value is formed in the resist, and this opening is uniformly shrunk using thermal flow deformation to use the shrunk width of the opening as the interval between floating gates (for example, Japanese Patent Laid-Open Publication No. 2004-342894).
In the technique disclosed in Japanese Patent Laid-Open Publication No. 2004-342894, a heat treatment step is required to make the floating gate interval smaller than the lithographic limit value, which increases the manufacturing costs. Furthermore, in this technique, it is not possible to make the gate size (gate length) smaller than the lithographic limit value.
Thus, the formation of a pattern having a size smaller than the limit size that can be made by lithography has a problem in that it is difficult to obtain both desirable line size and desirable space size.